The present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for improving integrated circuit device performance using hybrid crystal orientations.
Complementary metal-oxide-semiconductor (CMOS) technology is the predominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Conventional CMOS technology generally employs silicon (Si) wafers as the starting material for volume production. These silicon wafers generally have a single crystal surface that is (100) oriented; i.e., the normal to the silicon wafer surface is in the [100] direction. Hence, conventional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) formed on (100) silicon wafers have a gate dielectric-channel interface plane that is in the (100) plane of the silicon substrate.
Electrons are known to have a relatively high mobility for a (100) Si surface orientation, whereas holes are known to have high mobility for a (110) surface orientation. More specifically, hole mobility values for (100) Si are roughly two to four times lower than the corresponding electron mobility values for this crystallographic orientation. As a result, n-type devices formed in (100) silicon have a higher carrier mobility than p-type devices (with comparable device geometry) formed in (100) silicon. Thus, in order to compensate for this discrepancy, PFET devices are typically designed with larger widths with respect to NFET devices in order to balance the PFET pull-up currents against the NFET pull-down currents and achieve uniform circuit switching.
On the other hand, hole mobilities for (110) Si are about twice as high than for (100) Si. Consequently, PFETs formed on a (110) Si surface will exhibit significantly higher drive currents than PFETs formed on a (100) surface. Unfortunately, electron mobilities for (110) Si surfaces are significantly degraded as compared to (100) Si surfaces. A comparison of electron and hole mobilities with respect to different crystal orientations is illustrated in FIG. 1. As will be noted from a speed perspective, a (110) Si surface is optimal for PFET devices because of the excellent hole mobility, while a (100) Si surface is optimal for NFET devices because of the excellent electron mobility.
In order to fully utilize the advantage of the carrier mobility dependence on substrate orientation, various technologies of fabricating CMOS on hybrid substrates with different crystal orientations have been developed, in which the NFETs are manufactured at (100) surface orientations within the hybrid substrates, while the PFETs are manufactured at (110) surface orientations within the hybrid substrate. Because both types of devices (NFETs and PFETs) are operating with their respective carriers at peak mobilities, the resulting CMOS has overall higher speed and transconductance (or gain) as compared with a traditional CMOS structure where both the NFET and PFET are located on the same (100) substrate. In this application, the main benefit is the optimization of device performance since the PFET devices, being located on (110) substrates, now have comparable carrier mobilities as the (100) NFET devices.
In other instances, however, maximization of carrier mobility is not the desired goal of certain semiconductor devices. Thus, it is also desirable to be able to fabricate semiconductor devices having, for example, offset characteristics with respect to one another, and in a manner that conserves device real estate.